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Asic design of all digital pll{u2019}s for processors-clock generation / Ezzeldin Omar Ahmed Hussein Hamed ; Supervised Serag E. D. Habib , Hanan A. Kamal

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Ezz Eldin Omar Ahmed Hussein Hamed , 2012Description: 61 P. : facsimiles ; 30cmOther title:
  • تصميم دائرة رقمية بالكامل لضبط طور إشارة الساعة لمشغل دقيق [Added title page title]
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  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication Summary: All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors{u2019} clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications
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Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2012.Ez.A (Browse shelf(Opens below)) Not for loan 01010110064836000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2012.Ez.A (Browse shelf(Opens below)) 64836.CD Not for loan 01020110064836000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication

All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors{u2019} clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications

Issued also as CD

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